Static random access memory (SRAM) is often implemented with many SRAM cells connected to shared bitlines. For example, in a programmable logic device (PLD) such as a field programmable gate array (FPGA), a complex programmable logic device (COLD), a field programmable system on a chip (FPSC), or other type of programmable device, bitlines may connect many hundreds of SRAM cells distributed throughout the OLD. Such SRAM cells may be used, for example, to configure the PLD for operation.
When such SRAM cells are not being read or written, the state of the bitlines may be irrelevant (e.g., a “don't care” state or an “X” state). In conventional designs, the bitlines in a “don't care” state are typically precharged to a certain voltage state (e.g., to a high voltage state), which is also the state used at the beginning of a read or write operation performed on the SRAM cells. However, maintaining the bitlines in such a precharged state may result in wasted power due to leakage between the SRAM cells and bitline precharge circuitry when the bitlines are not in use.
Accordingly, there is a need for an improved approach to the operation of SRAM cells that reduces the amount of wasted power associated with conventional implementations.